september 2013 1 ?2013 integrated device technology, inc. dsc-2946/13 features high-speed address/chip select time ? military: 25/35/45/55/70/85/100ns (max.) ? commercial/industrial: 20/25/35ns (max.) low power only low-power operation battery backup operation ? 2v data retention produced with advanced high-performance cmos technology input and output directly ttl-compatible available in standard 28-pin (300 or 600 mil) ceramic dip, 28-pin (300 mil) soj military product compliant to mil-std-883, class b description the idt 71256 is a 262,144-bit high-speed static ram organized as 32k x 8. it is fabricated using high-performance, high-reliability cmos technology. functional block diagram address access times as fast as 20ns are available with power consumption of only 350mw (typ.). the circuit also offers a reduced power standby mode. when cs goes high, the circuit will automatically go to and remain in, a low-power standby mode as long as cs remains high. this capability provides significant system level power and cooling savings. the low-power (l) version also offers a battery backup data retention capability where the circuit typically consumes only 5 w when operating off a 2v battery. the idt71256 is packaged in a 28-pin (300 or 600 mil) ceramic dip, a 28-pin 300 mil soj providing high board level packing densities. the idt71256 military ram is manufactured in compliance with the latest revision of mil-std-883, class b, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. cmos static ram 256k (32k x 8-bit) idt71256s IDT71256L a 0 address decoder 262,144 bit memory array i/o control 2946 drw 01 input data circuit we cs v cc gnd a 14 i/o 0 i/o 7 control circuit oe ,
2 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges absolute maximum ratings (1) pin configurations dip/soj top view truth table (1) pin descriptions name description a 0 - a 14 address inputs i/o 0 - i/o 7 data input/output cs chip select we write enable oe output enable gnd ground v cc power 2 946 tbl 01 capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is determined by device characterization, but is not production tested. note: 1. h = v ih , l = v il , x = don't care. we cs oe i/o function x h x high-z standby (i sb ) xv hc x high-z standby (i sb1 ) h l h high-z output disabled hlld out read data llxd in write data 2 946 tbl 02 note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol rating com'l. ind. mil. unit v te rm terminal voltage with resp ect to gnd -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 v t a operating te m p e ra tu r e 0 to +70 -40 to +85 -55 to +125 o c t bias te m p e ra tu r e under bias -55 to +125 -55 to +125 -65 to +135 o c t stg storage te m p e ra tu r e -55 to +125 -55 to +125 -65 to +150 o c p t power dissipation 1.0 1.0 1.0 w i out dc output current505050ma 2946 tbl 03 symbol parameter (1 ) conditions max. unit c in input capacitance v in = 0v 11 pf c i/ o i/o capacitance v out = 0v 11 pf 2946 tbl 04 2946 drw 02 5 6 7 8 9 10 11 12 gnd 1 2 3 4 24 23 22 21 20 19 18 17 d28-3 d28-1 so28-5 13 14 28 27 26 25 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v cc a 14 we a 13 a 8 a 10 a 11 oe a 12 cs i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 a 9 16 15
6.42 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges 3 recommended operating temperature and supply voltage recommended dc operating conditions note: 1. v il (min.) = ?3.0v for pulse width less than 20ns, once per cycle. grade temperature gnd vcc military -55 o c to +125 o c 0v 5v 10% industrial -40 o c to +85 o c 0v 5v 10% commercial 0 o c to +70 o c 0v 5v 10% 2 946 tbl 05 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 v v il input low voltage -0.5 (1) ____ 0.8 v 2946 tbl 06 dc electrical characteristics (1,2) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc - 0.2v) 0 2 l / s 6 5 2 1 75 2 l / s 6 5 2 1 75 3 l / s 6 5 2 1 75 4 l / s 6 5 2 1 7 l o b m y sr e t e m a r a p r e w o p. l ' m o c d n i & l ' m o c d n i & . l i m. l ' m o c d n i & . l i m. l i m t i n u i c c t n e r r u c g n i t a r e p o c i m a n y d s c < v l i n e p o s t u p t u o , v c c f , . x a m = x a m ) 2 ( s _ _ _ __ _ _ _ 0 5 1 _ _ _ _ 0 4 15 3 1 a m l5 3 15 2 10 3 15 1 10 2 15 1 1 i b s t n e r r u c y l p p u s r e w o p y b d n a t s , ) l e v e l l t t ( s c > v h i v , c c , . x a m = f = f , n e p o s t u p t u o x a m ) 2 ( s _ _ _ __ _ _ _ 0 2 _ _ _ _ 0 20 2 a m l 3 3333 3 i 1 b s t n e r r u c y l p p u s r e w o p y b d n a t s l l u f , ) l e v e l s o m c ( s c > v c h , v c c 0 = f , . x a m = s _ _ _ __ _ _ _ 0 2 _ _ _ _ 0 20 2 a m l6 . 06 . 05 . 16 . 05 . 15 . 1 7 0 l b t 6 4 9 2 5 5 l / s 6 5 2 1 70 7 l / s 6 5 2 1 75 8 l / s 6 5 2 1 70 0 1 l / s 6 5 2 1 7 l o b m y sr e t e m a r a pr e w o p. l i m. l i m. l i m. l i mt i n u i c c t n e r r u c g n i t a r e p o c i m a n y d s c < v l i n e p o s t u p t u o , v c c f , . x a m = x a m ) 2 ( s5 3 15 3 15 3 15 3 1 a m l5 1 15 1 15 1 15 1 1 i b s t n e r r u c y l p p u s r e w o p y b d n a t s , ) l e v e l l t t ( s c > v h i v , c c , . x a m = f = f , n e p o s t u p t u o x a m ) 2 ( s0 20 20 20 2 a m l3333 i 1 b s t n e r r u c y l p p u s r e w o p y b d n a t s l l u f , ) l e v e l s o m c ( s c > v c h , v c c 0 = f , . x a m = s0 20 20 20 2 a m l5 . 15 . 15 . 15 . 1 8 0 l b t 6 4 9 2 notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc , all address inputs are cycling at f max ; f = 0 means no address pins are cycling.
4 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges ac test conditions *includes scope and jig capacitances figure 2. ac test load (for t clz , t olz , t chz, t ohz , t ow , and t whz ) figure 1. ac test load inp ut pulse le ve ls inp ut rise /fall time s inp ut timing re fe re nce le ve ls output reference levels ac test load gnd to 3.0v 5ns 1.5v 1.5v see figures 1 and 2 2 946 tbl 09 2946 drw 04 480 ? 255 ? 30pf* data out 5v , 2946 drw 05 480 ? 255 ? 5pf* data out 5v , dc electrical characteristics (v cc = 5.0v 10%) data retention characteristics over all temperature ranges (l version only) (v lc = 0.2v, v hc = v cc - 0.2v) notes: 1. t a = +25c. 2. t rc = read cycle time. 3. this parameter is guaranteed by device characterization, but is not production tested. symbol parameter test conditions idt71256s IDT71256L unit min. typ. max. min. typ. max. |i li | input leakage current v cc = max., v in = gnd to v cc mil. com"l & ind. ____ ____ ____ ____ 10 5 ____ ____ ____ ____ 5 2 a |i lo | output leakage current v cc = max., cs = v ih , v out = gnd to v cc mil. com"l & ind. ____ ____ ____ ____ 10 5 ____ ____ ____ ____ 5 2 a v ol output low voltage i ol = 8ma, v cc = min. ____ ____ 0.4 ____ ____ 0.4 v i ol = 10ma, v cc = min. ____ ____ 0.5 ____ ____ 0.5 v oh output high voltage i oh = -4ma, v cc = min. 2.4 ____ ____ 2.4 ____ ____ v 2946 tbl 1 0 typ. (1 ) v cc @ max. v cc @ symbol parameter test condition min. 2.0v 3.0v 2.0v 3.0v unit v dr v cc for data retention ____ 2.0 ____ ____ ____ ____ v i ccdr data retention current mil. com'l. & ind. ____ ____ ____ ____ ____ ____ 500 120 800 200 a t cdr chip deselect to data retention time cs > v hc 0 ____ ____ ____ ____ ns t r (3) operation recovery time t rc (2) ____ ____ ____ ____ ns 2946 tbl 11
6.42 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges 5 ac electrical characteristics (v cc = 5.0v 10%, all temperature ranges) low v cc data retention waveform 2946 drw 06 data retention mode 4.5v 4.5v v dr 2v v ih v ih t r t cdr v cc cs v dr notes: 1. 0 to +70c or -40 to +85c temperature range only. 2. this parameter is guaranteed by device characterization, but is not production tested. 3. ?55c to +125c temperature range only. l o b m y sr e t e m a r a p 0 2 l 6 5 2 1 7 ) 1 ( 5 2 s 6 5 2 1 7 ) 3 ( 5 2 l 6 5 2 1 7 5 3 s 6 5 2 1 7 ) 3 ( 5 3 l 6 5 2 1 7 5 4 s 6 5 2 1 7 ) 3 ( 5 4 l 6 5 2 1 7 ) 3 ( t i n u . n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m e l c y c d a e r t c r e m i t e l c y c d a e r0 2 _ _ _ _ 5 2 _ _ _ _ 5 3 _ _ _ _ 5 4 _ _ _ _ s n t a a e m i t s s e c c a s s e r d d a _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 5 3 _ _ _ _ 5 4s n t s c a e m i t s s e c c a t c e l e s p i h c _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 5 3 _ _ _ _ 5 4s n t z l c ) 2 ( z - w o l n i t u p t u o o t t c e l e s p i h c5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t z h c ) 2 ( z - h g i h n i t u p t u o o t t c e l e s e d p i h c _ _ _ _ 0 1 _ _ _ _ 1 1 _ _ _ _ 5 1 _ _ _ _ 0 2s n t e o d i l a v t u p t u o o t e l b a n e t u p t u o _ _ _ _ 0 1 _ _ _ _ 1 1 _ _ _ _ 5 1 _ _ _ _ 0 2s n t z l o ) 2 ( z - w o l n i t u p t u o o t e l b a n e t u p t u o2 _ _ _ _ 2 _ _ _ _ 2 _ _ _ _ 0 _ _ _ _ s n t z h o ) 2 ( z - h g i h n i t u p t u o o t e l b a s i d t u p t u o 282 0 125 1 _ _ _ _ 0 2s n t h o e g n a h c s s e r d d a m o r f d l o h t u p t u o5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n e l c y c e t i r w t c w e m i t e l c y c e t i r w0 2 _ _ _ _ 5 2 _ _ _ _ 5 3 _ _ _ _ 5 4 _ _ _ _ s n t w c e t i r w - f o - d n e o t t c e l e s p i h c5 1 _ _ _ _ 0 2 _ _ _ _ 0 3 _ _ _ _ 0 4 _ _ _ _ s n t w a e t i r w - f o - d n e o t d i l a v s s e r d d a5 1 _ _ _ _ 0 2 _ _ _ _ 0 3 _ _ _ _ 0 4 _ _ _ _ s n t s a e m i t p u - t e s s s e r d d a0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t p w h t d i w e s l u p e t i r w5 1 _ _ _ _ 0 2 _ _ _ _ 0 3 _ _ _ _ 5 3 _ _ _ _ s n t r w e m i t y r e v o c e r e t i r w0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t w d p a l r e v o e m i t e t i r w o t a t a d1 1 _ _ _ _ 3 1 _ _ _ _ 5 1 _ _ _ _ 0 2 _ _ _ _ s n t z h w ) 2 ( z - h g i h n i t u p t u o o t e l b a n e e t i r w _ _ _ _ 0 1 _ _ _ _ 1 1 _ _ _ _ 5 1 _ _ _ _ 0 2s n t h d e m i t e t i r w m o r f d l o h a t a d0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t w o ) 2 ( e t i r w - f o - d n e m o r f e v i t c a t u p t u o5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n 2 1 l b t 6 4 9 2
6 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges ac electrical characteristics (v cc = 5.0v 10%, military temperature ranges) notes: 1. -55 to +125c temperature range only. 2. this parameter is guaranteed by device characterization, but is not production tested. symbol parameter 71256s55 (1 ) 71256l55 (1) 71256s70 (1 ) 71256l70 (1 ) 71256s85 (1 ) 71256l85 (1 ) 71256s100 (1 ) 71256l100 (1 ) unit min. max. min. max. min. max. min. max. read cycle t rc read cycle time 55 ____ 70 ____ 85 ____ 100 ____ ns t aa address access time ____ 55 ____ 70 ____ 85 ____ 100 ns t acs chip select access time ____ 55 ____ 70 ____ 85 ____ 100 ns t cl z (2 ) chip select to output in low-z 5 ____ 5 ____ 5 ____ 5 ____ ns t chz (2) chip deselect to output in high-z ____ 25 ____ 30 ____ 35 ____ 40 ns t oe output enable to output valid ____ 25 ____ 30 ____ 35 ____ 40 ns t olz (2) output enab le to output in low-z 0 ____ 0 ____ 0 ____ 0 ____ ns t ohz (2 ) output disab le to output in high-z 0 25 0 30 ____ 35 ____ 40 ns t oh output hold from address change 5 ____ 5 ____ 5 ____ 5 ____ ns write cycle t wc write cycle time 55 ____ 70 ____ 85 ____ 100 ____ ns t cw chip select to end-of-write 50 ____ 60 ____ 70 ____ 80 ____ ns t aw address valid to end-of-write 50 ____ 60 ____ 70 ____ 80 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 40 ____ 45 ____ 50 ____ 55 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t dw data to write time overlap 25 ____ 30 ____ 35 ____ 40 ____ ns t whz (2) write enable to output in high-z ____ 25 ____ 30 ____ 35 ____ 40 ns t dh data hold from write time ( we )0 ____ 0 ____ 0 ____ 0 ____ ns t ow (2) output active from end-of-write 5 ____ 5 ____ 5 ____ 5 ____ ns 2946 tbl 13
6.42 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges 7 timing waveform of read cycle no. 2 (1,2,4) notes: 1. we is high for read cycle. 2. device is continuously selected, cs is low. 3. address valid prior to or coincident with cs transition low. 4. oe is low. 5. transition is measured 200mv from steady state. timing waveform of read cycle no. 1 (1) address cs oe data out t rc t aa t oh t oe t acs t clz (5) t olz (5) 2946 drw 07 t chz (5) t ohz (5) 2946 drw 08 address data out t rc t aa t oh t oh , timing waveform of read cycle no. 2 (1,3,4) cs data out t acs t clz (5) 2946 drw 09 t chz (5)
8 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges timing waveform of write cycle no. 1 ( we controlled timing) (1,2,4,6) notes: 1. a write occurs during the overlap of a low cs and a low we . 2. t wr is measured from the earlier of cs or we going high to the end of the write cycle. 3. during this period, i/o pins are in the output state so that the input signals must not be applied. 4. if the cs low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. transition is measured 200mv from steady state. 6. if oe is low during a we controlled write cycle, the write pulse width must be the larger of t wp or (t whz +t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short as the specified t wp . for a cs controlled write cycle, oe may be low with no degradation to t cw . timing waveform of write cycle no. 2 ( cs controlled timing) (1,2,4) cs 2946 drw 10 t aw t wr t dw data in address t wc we t wp t dh data out t wz t t as (5) (3) oe (3) (6) ow t ohz (5) t wr cs 2946 drw 11 t aw t dw data in address t wc we t cw t dh2 as t t (6)
6.42 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges 9 ordering information ? commercial & industrial ordering information ? military x power speed xxx package x process/ temperature range b military (?55c to +125c) compliant to mil-std-883, class b td d 300 mil cerdip (d28-3) 600 mil cerdip (d28-1) 25 35 45 55 70 85 100 s l standard power low power device type 71256 speed in nanoseconds 2946 drw 12 xxx x power xx speed xxx package x process/ temperature range blank i commercial (0c to +70c) industrial (-40c to +85c) g 300 mil soj (so28-5) 20 25 35 l low power only device type 71256 speed in nanoseconds 2946 drw 13 x y green blank 8 tube or tray tape and reel x
10 idt71256s/l cmos static ram 256k (32k x 8-bit) military, commercial, and ind ustrial temperature ranges datasheet document history 11/4/99: updated to new format pp. 1?5, 9 added industrial temperature range offerings pg. 1 removed 30, 120, and 150ns military and 45ns commercial speed grade offerings. pg. 2 removed p28-2 package from dip/soj top view pg. 3 removed 30ns and 45ns (commercial only) speed grade offerings from dc electrical table revised notes and footnotes pg. 5 removed 30ns speed grade offering from ac electrical table revised notes and footnotes pg. 6 expressed military temperature range on ac electrical table revised notes and footnotes pg. 8 removed note 1 and renumbered notes and footnotes pg. 9 revised ordering information and presented by temperature range offering pg. 10 added datasheet document history 08/09/00: not recommended for new designs 02/01/01: remove "not recommended for new designs" 11/15/06: pg. 3 changed power limits for commercial and industrial. refer to pcn sr-0602-03. added restricted hazardous substance devce to ordering information. 11/01/08: pg. 2,9 corrected typo on pin 21 in 32-pin lcc diagram. updated the ordering information by removing the "idt" notation. 04/28/11: pg. 1, 2, 5, 9 added 20ns to industrial offering. obsoleted 28-pin 600 mil, 32-pin lcc and added tape and reel to ordering information and updated description of restricted hazardous substance device to green. 09/26/13: pg. 1 in the description: removed idt?s reference to fabrication and removed the sentence " in the full standby mode, the low-power device consumes less than 15w, typically". the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or ipchelp@idt.com san jose, ca 95138 408-284-8200 800-345-7015 fax: 408-284-2775 www.idt.com
|
